Table of Contents
The x86 architecture is the generic name for a multi-vendor 16-bit, 32-bit, and most recently 64-bit architecture. It was originally developed by Intel in the 8086 series of CPU, extended to 32-bit by Intel in the 80386 CPU, and extended by AMD to 64 bits in the Opteron and Athlon 64 CPU lines. While as of 2007, Intel and AMD are the highest volume manufacturers of x86 CPUs, many other vendors have also manufactured x86 CPUs. Generally the manufacturers have cross-licensed (or copied) major improvements to the architecture, but there are some unique features present in many of the implementations.
The x86 architecture has a variable instruction size that allows for moderate code compression while also allowing for very complex operand combinations as well as a very large instruction set size with many extensions. Instructions generally vary from zero to three operands with only a single memory operand allowed.
Different processors have different recommendations for the NOP (no operation) instructions used for padding in code. Padding is commonly
performed to align loop boundaries to maximize performance, and it is key that the
padding itself add minimal overhead. While the one-byte NOP 90h is standard across all x86 implementations, more recent generations
of processors recommend different variations for longer padding sequences for optimal
performance. Most processors that claim a 686 (e.g. Pentium Pro) generation or newer
featureset support the “long”
NOP opcode 0Fh 1Fh, although this opcode was undocumented
until recently. Older processors that do not support these dedicated long NOP opcodes
generally recommended alternative longer NOP sequences; while these sequences work as
NOPs, they can cause decoding inefficiencies on newer processors.
Because of the various NOP recommendations, the code generated by the Yasm
ALIGN directive depends on both the execution mode
(BITS) setting and the processor selected by the
CPU directive (see Section 21.2.1).
Table 21.1 lists the various combinations of
generated NOPs.
Table 21.1. x86 NOP Padding Modes
BITS |
CPU |
Padding |
|---|---|---|
|
|
Any |
16-bit short NOPs |
|
|
None given, or less than |
32-bit short NOPs (no long NOPs) |
|
|
|
Intel guidelines, using long NOPs |
|
|
|
AMD K10 guidelines, using long NOPs |
|
|
None |
Intel guidelines, using long NOPs |
|
|
|
Intel guidelines, using long NOPs |
|
|
|
AMD K10 guidelines, using long NOPs |
In addition, the above defaults may be overridden by passing one of the options in
Table 21.2 to the CPU directive.